1) Field of the Invention
The invention relates to a process for providing a rough Si surface on a Si sidewall during preparation of a DT DRAM, to obtain DT surface area enhancement for a DT DRAM by creating a rough oxide etch mask, based on an anneal/oxidation of deposited amorphous Si (a-Si) on a SiN liner. The process permits a process/integration scheme which allows the integration of this process into a collar process utilizing SiO2 or SiN as the collar material.
2) Description of the Prior Art
It is known that node capacitance requirements for DT DRAM devices does not shrink with decreasing groundrule/cell size. Moreover, extendability of current processes such as wet bottle and deeper trench etchings does not provide sufficient surface area enhancement for the DT DRAM devices.
For example, the use of sub-micron features for fabrication of a DRAM device in which the capacitor of the DRAM device is a stacked capacitor structure creates problems when attempts are made to increase the capacitance. In this connection, it should be noted that a DRAM cell is generally comprised of a stacked capacitor structure that overlies a transfer gate transistor, and is connected to the source of the transfer gate transistor. The decreasing size of the transfer gate transistor limits the dimensions of the stacked capacitor structure. Therefore, to increase the capacitance of the stacked capacitor structure, which is comprised of two electrodes separated by a dielectric layer, the thickness of the dielectric layer must be decreased or the area of the capacitor must be increased. However, advancement of the DRAM technology to densities of 64 million cells per chip or greater results in a cell in which a smaller transfer gate transistor is used, thereby resulting in less of an overlying area for placement of overlying stacked capacitor structures.
U.S. Pat. No. 5,340,763 describes a method of maintaining or increasing stacked capacitor structure capacitance, while decreasing the lateral dimension of the capacitor by use of a rough or hemispherical grained (HSG) polysilicon layers. Nevertheless, the capacitance increase realized in this patent is limited by subjecting only the top surface of the polysilicon lower electrode to the HSG polysilicon deposition and etch procedure, thereby leaving the sides of the polysilicon lower electrode flat.
Hemispherical grained (HSG) polysilicon layers have also been used as overlying layers on conventional polysilicon structures, as described in U.S. Pat. No. 5,444,653. This patent specifically describes a storage node, or lower electrode of a stacked capacitor structure, in which the surface area of a polysilicon lower electrode structure is increased by deposition of an HSG polysilicon layer on an insulator layer, which overlies the top surface of the lower electrode structure. Subsequent etching procedures result in a transfer of the roughened surface created by the HSG polysilicon layer to only the top surface of the polysilicon lower electrode structure. The roughened, top surface of the polysilicon lower electrode, with increased surface area results in a capacitance increase for the subsequent capacitor structure.
U.S. Pat. No. 6,037,220 disclose a process for increasing the surface area of a polysilicon lower electrode, or storage node electrode, by forming an HSG polysilicon layer only on the sides of the storage node electrode, while maintaining a flat, or non-roughened, top surface. This configuration is a result of using a silicon oxide hard mask, overlying the top surface of the lower electrode structure, therefore accepting the HSG polysilicon deposition. The use of the silicon oxide hard mask, prevents the deleterious attack of the polysilicon lower electrode structure, during an HSG polysilicon etch back procedure, performed to remove unwanted HSG polysilicon from non-capacitor regions.
This patent also describes an iteration in which the HSG polysilicon-silicon oxide, hard mask features are prepared on the top surface of the polysilicon lower electrode structure, then used as a mask, to remove polysilicon from the spaces exposed between the HSG polysilicon-silicon oxide features. The etch process results in a roughened, polysilicon lower electrode, top surface, and along with the HSG polysilicon coated sidewalls, provide greater surface area increases than counterparts fabricated with only roughened sides, or with only a roughened top surface.
U.S. Pat. No. 6,232,171 B1 disclose a method for enlarging the sidewall surface of a deep trench with improved process precision (without depending upon the differential etch rate between doped and undoped silicon) so that the sidewall surface enlargement is optimally and most effectively controlled within a lower portion of the sidewall where a tapered-down trench diameter distribution is encountered due to the reduced trench opening on a deep sub-micron semiconductor device and the large aspect ratio (length-to-diameter ratio) of the vertically oriented trench. When this method is incorporated into a process for making deep trench capacitors, the method comprises:
(1) forming a deep trench into an active (i.e., conducting) region in a substrate;
(2) filling the deep trench with a dielectric material, typically an oxide;
(3) etching the dielectric material down to a predetermined depth;
(4) forming a thin oxidative layer, using a thermal oxidation procedure, on the sidewall of the trench above the dielectric material and on the top surface around the trench for stress relief;
(5) forming a nitride layer covering the thin oxide layer;
(6) using an anisotropic etching procedure to form a nitride sidewall spacer from the nitride layer;
(7) removing the dielectric material by a selective wet etching to expose the sidewall of the trench below the nitride sidewall spacer;
(8) using the nitride sidewall spacer as a mask, thermally oxidizing the portion of the substrate behind the sidewall of the trench below the nitride sidewall spacer to a predetermined penetration; and
(9) removing the oxidized silicon sidewall and the nitride sidewall spacer, either simultaneously or separately.
In view of the fact that node capacitance requirements for DT DRAM technology does not shrink with decreasing groundrule/cell size, and in view of the fact that extendability of current processes such as wet bottle and deeper trench etching do not provide sufficient surface area enhancement, there is a need for additional processes for surface area increases when preparing DT DRAM devices.
One object of the present invention is to provide a process for surface area enhancement or increases for DT DRAM devices of densities of 64 million cells per chip, or greater.
Another object of the present invention is to provide a process for surface area enhancement or increases for DT DRAM devices utilizing a rough Si surface that is a rough mask material that can be used to transfer the pattern to the Si sidewall of the DT DRAM device.
A further object of the present invention is to provide a process for surface area enhancement for DT DRAM devices utilizing a process to create a rough oxide etch mask, based on the anneal/oxidation of deposited amorphous Si (a-Si) on a SiN liner.
A yet further object of the present invention is to provide a process integration scheme when providing surface area enhancement of a DT DRAM device which allows integration of this process into a collar process using SiO2 or SiN as a collar material.